Active projects

Analysis and improvement techniques for robustness and security of nanometer circuits in the presence of attacks, defects, variability and aging.

Nowadays Integrated circuits (ICs) are able to integrate on the same substrate an increasing number of devices able to perform complex heterogeneous functions (digital processing, embedded memories and digital-analog mixed-signal circuits) . However, the continued demand for better performance of these ICs leads to a dramatic increase in the effects of miniaturization. Among the main causes that threaten reliability are manufacturing defects, the variability of both the manufacturing process itself (P) and operating conditions of the circuit (voltage and temperature, VT) and finally, aging (A) caused by the wearout due to its own activity. In this context, implementation of new strategies that improve robustness and assure quality specifications of the final product are neeeded. 

To continue the level of miniaturization, one of the most promising recent alternative is stacking dice of silicon integrated circuits in the so called 3D integration. However, the introduction of these involves the emergence of new challenges that will change the paradigms of the test. In fact, the International Technology Roadmap for Semiconductors update of 2012 (ITRS 2012) identifies the need of verifying 3D circuits as one of the key drivers of the test, and the reliability of TSVs as one of its greatest challenges.
Moreover, in certain applications the ICs process information where security is critical. In this sense, safety in Critical Security Chip (CSC) needs constant improvement against physical attack techniques. Specifically, the design of embedded detectors against attacks and the mitigation of the effects of aging on unclonable functions can be improved by using techniques well known in the field of test.
The proposed project focuses on the research and development of new strategies for improving the robustness and
security of ICs in the presence of attacks, faults, variability and aging.